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Method for reconstruction of the internal structure FPGA family from Xilinx CoolRunner bit sequence to boot

Keywords:

V.S. Eskov


The article discusses FPGA family CoolRunner XPLA3, FPGA architecture of this family. The architecture is typical of the FPGA and CPLD includes function blocks (FB) and the input-output block (IOB), connected by a high-speed switching matrix ZIA (Zero-power Interconnect Array). Also focus on the structure of the boot bit sequence, it has a block structure. At the beginning of the boot is a bit sequence header that contains information about the time the file was created and the type of FPGA. Following are some of the same type of blocks, which contain information about the functional blocks. Based on these data, the technique has been the definition of the elements of architecture FPGA. With the use of this technique is possible to develop software recover the internal structure of FPGA families CoolRunner XPLA3.
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