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Hardware-levelbarriersynchronization implementation formesh-connected multicomputers

Keywords:

I.V. Zotov, A.A. Burmaka, R.V. Bredikhin, Yu.O. Sukhochev


The development and investigation of hardware-level methods for barrier synchronization between parallel processes residing in multicomputers is a crucial focus during several last years. The usage of a virtual bit-slice coordinating environment distributed between the processors of a multicomputer such that it provides fast barrier state signal interchange with no limitation on the barrier group configuration and/or the total count of barriers in a parallel program is a prospective research domain. In the present paper, the principals of organization of barrier synchronization between parallel processes in arbitrary dimension mesh-connected multicomputersbased on the usage of a virtual bit-slice coordinating environment are formulated. The environment topology construction rules are stated together with the virtualization principals aimed at the elimination of the limitations on the co-residing barrier count. Virtual slice switch ordering scheme that makes it possible to establish a parallel-pipelined barrier control binary signal interchange mode is sketched. The coordinating environment clocking mechanism is featured which takes into account the presence of a set of virtual slices.
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June 24, 2020
May 29, 2020

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