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A new method of gate dielectric degradation analysis in nigh-speed field-effect transistor


V.E. Drach – Ph. D. (Eng.), Associate Professor, EIU1-KF, Kaluga branch of the Bauman MSTU. E-mail:
A.V. Rodionov – Ph. D. (Eng.), Associate Professor, EIU2-KF, Kaluga branch of the Bauman MSTU. E-mail:

CMOS technology is being developed fast and nowadays is being considered as an advanced means of manufacturing the ultra high frequency range devices. For years, various transient phenomena in MOS devices have been observed and been explained as the consequence of charge and/or discharge of the border traps, e.g. the hysteresis of the HFCV, the current spikes in the MOS capacitors, the current DLTS (deep level transient spectroscopy), the charge pumping current in the varied frequency charge pumping measurements, and various current transients, etc. These transient observations are used to study the nature of border traps and to estimate the effective density of border traps. In this paper, we report a new Id(Vg) shift phenomenon observed in high electrical-field stressed MOS transistors. Similar to the hysteresis observed in HFCV, we believe this observation is the result of the charging and/or discharging of border traps, and, in particular, the slow border traps. In this article, the Id(Vg) shift and the slow border trap are systematically studied, including the origin of the Id(Vg) shift, the physical nature and significance of the Id(Vg) shift, the charging characteristics and process of the slow border traps, influencing factors, and the parameters used to characterize the Id(Vg) shift. Finally, the possibility to use the Id(Vg) shift as a convenient tool to study the slow border traps and a degradation monitor is discussed. The main results and conclusions of this paper are confirmed by the gate geometry manifold of samples used in the experiments.

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