V.E. Drach – Ph. D. (Eng.), Associate Professor, EIU1-KF, Kaluga branch of the Bauman MSTU. E-mail: firstname.lastname@example.org
A.V. Rodionov – Ph. D. (Eng.), Associate Professor, EIU2-KF, Kaluga branch of the Bauman MSTU. E-mail: email@example.com
Today, the development of telecommunication and computing devices depends on semiconductor industry advances. The growth of the semiconductor industry is based upon an observation by Gordon Moore (co-founder and Chairman Emeritus of Intel Corporation), who predicted that the number of transistors on an integrated circuit doubles approximately every two years – an observation that has since become known as Moore's Law. This remarkable accomplishment has been achieved through a phenomenon known as scaling – a systematic shrinkage of the single device dimensions. In the main this has been achieved by advancements in device fabrication techniques and in particular, advancements in lithographic techniques that allow ever-decreasing dimensions to be defined. However, despite the historical success of scaling, it is now obvious that the continued performance enhancements in CMOS circuits that the industry has become accustomed to, cannot be achieved by scaling alone. Silicon planar MOSFETs are fast approaching their scaling limitations and new device structures are being investigated with the intention to replace the current planar silicon-only MOSFET. The alternative devices are discussed, such as tunneling FET, nano-electro-mechanical switch, single electron transistor, Mott FET, quantum cellular automata, atomic switch, SpinFET, graphene based transistors. All the alternative devices could be divided into two classes: charge-based devices and non-charge devices. New materials, ideas and technologies are being discussed. This paper is an overview of the leading advanced nanoelectronic devices, noting key features and potential challenges.
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