N.V. Astakhov – Ph. D. (Eng.), Associate Professor, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University
A.V. Bashkirov – Ph. D. (Eng.), Associate Professor, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University
M.V. Horoshaylova – Post-graduate Student, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University
S.Ju. Beleckaja – Professor, Department of Systems of Automated Design and Information Systems,
Voronezh State Technical University
This paper describes an approach to the design of the decoder, which is designed specifically for implementation on FPGAs. FFT-BP mixed domain decoding algorithm is used that does not exclude the multiplier blocks. Presented in part parallel to the extension of the mixed domain decoder that works for structured codes. Next, carefully analyzed the impact on the final precision of decoding per-formance. Through modeling and synthesis of the results shown to be advantageous to segment the data stream at the decoder portion 3 with different accuracy. The results also contribute to the accuracy of choice for maximum performance or for some compromise performance complexity.
The effective implementation of the partially parallel to GF (q) -LDPC decoder designed for FPGA devices. This design is a continuation of a consistent architecture. Partially parallel implementation can achieve higher throughput and allows to reach a compromise throughput complexity. The effectiveness of the implementation representation is based on the balanced use of all types of FPGA resources, in particular, the use of units of multipliers.
An important issue discussed in this article, is a method of communication and the quantization precision. It is shown that the length of the word decoder posts projected to be selected separately for the logarithmic domain (Wl) and the field of probability (Wp) of the data stream decoder. In addition, other precision should be selected for non-normalized messages (Wre). The experimental results that make it easy to message bit and suggest that the length of the proposed differentiation of the word is correct. Recommendations regarding the selection of accuracy were also given for the three parts of the decoder data streams. In particular, the decoder accuracy Wl = 8, 20 = Wre and Wp = 14 achieves near optimal performance, whereas the FPGA resources are significantly reduced in comparison with the proposed solution without differentiation accuracy.
- D.J.C. MacKay. Good error-correcting codes based on very sparse matrices // IEEE Trans. Inf. Theory. 1999.
- Huang J., Zhou S., and Willett P. Nonbinary LDPC coding for multicarrier underwater acoustic communication // IEEE J. Sel. Areas Commun. 2008.
- Savin V. Min-Max decoding for non binary LDPC codes // IEEE Proc. of International Symposium on Information Theory. Toronto (Canada). 2008.
- Bashkirov A.V., Xoroshajlova M.V. Algoritmy' nizkoj slozhnosti dekodirovaniya i arxitektura dlya nedvoichny'x nizkoplotnostny'x kodov // Radiotexnika. 2016. № 6. S. 10−14.
- Bashkirov A.V., Muratov A.V., Xoroshajlova M.V., Sitnikov A.V., Ermakov S.A. Nizkoplotnostny'e kody' maloj moshhnosti dekodirovaniya // Radiotexnika. 2016. № 5. S. 32−37.