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Fault tolerant adder

DOI 10.18127/j20700814-201809-01


S.F. Tyurin - Dr.Sc.(Eng.), Professor, Department of Automation and Telemechanic, Perm National Research Polytechnic University; Professor, Department of Mathematical Support of Computer Systems, Perm State National Research University

In this paper, we investigate a binary adder performing the operation of one-bit summation taking into account the carry, which is the basis for Information-measuring and Control Systems. The CMOS circuit of such a binary adder is analyzed, which contains the sub-circuit of the realization of the sum and the sub-circuit of the implementation of the output carry, both the va-riables themselves and their inversions are necessary. A variant of the presence of only variables without their inversions is consi-dered, in this case a so-called classical mirror adder is obtained, when the inversion of the output carry is realized and it is used as an additional variable in the sub-circuit for implementing the sum inversion. In the article, the corresponding mathematical expressions describing the CMOS circuit of such an adder are obtained. In order to develop a fault-tolerant adder, it is proposed the sub-circuit output carry transistor redundancy since in this case the sub-circuit output carry satisfies the Mead–Conway constraints on the number of transistors in a consecutive chain, which can be no more than four. The sum sub- does not satisfy these restrictions, therefore, the corresponding decomposition of the sum sub-circuit into three sub-circuit satisfying the Mead–Conway constraints is proposed in the article. The corresponding mathematical transformation and the CMOS circuit of the converted adder are described. To confirm the correctness of the decomposition performed, the proposed CMOS circuit is simulated in the NI Multisim 10 environment of the National Instruments Electronics Workbench Group. The results of a comparative evaluation of the failure-free operation probability of the proposed decomposed adder circuit with redundant transistors and a triple adder circuit are described. It is shown that the proposed adder significantly benefits in reliability in comparison with the non-redundant adder, and also in comparison with the tripled variants. At the same time, the speed is not worse than the tripling adder.

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