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Challenges in IC metallization systems in sub-10 nm nodes

DOI 10.18127/j22250999-201902-05

Keywords:

S.V. Pahomov ‒ Post-graduate Student, MIREA ‒ Russian Technological University (Moscow, Russia)
Е-mail: 321ru@mail.ru


Integrated Circuits (ICs) scaling leads to significant challenges in multi-level metallization systems, that provides commutation of transistors and other active ICs elements. Transistor scaling leads to a decrease in delay times, while the delay time of the metallization system (defined as RC-delay, where R is the theresistance of conductors, C is the capacity) significantly increases after 14 nm node and reaches 80 % and more from the total signal delay. In addition to IC frequency restrictions, the metallization system becomes a source of a heat release and cross talk noise. This article discusses BEOL issues at 10, 7 and 5 nm technology nodes. The focus is on the challenges in metal conductors and barrier layers. It is shown that scaling of copper conductors at sub-10 nm nodes leads to significant increase in their resistance due to carrier scattering on the surfaces and crystallites boundaries. In this regard, the industry considers alternative conductor materials ‒ Co and Ru, which have a smaller electron mean free path and better electromigrationresistance. Co can also be used as a cap layer in Cu conductors to improve electromigration properties. Another key issue is the growing role of the metal barrier, which prevents the diffusion of atoms and copper ions into the dielectric. The barrier thickness is poorly scaled and becomes comparable to the size of the conductor itself, causing an increase in resistance. The main strategy at technology nodes less than 5 nm is the search for new metals, the use of which does not require a barrier layer. One of these candidates is Ru. The ways of via contacts resistance decreasing are discussed as well.

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