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Stochastic iterative decoding on factor graphs

DOI 10.18127/j00338486-201906(8)-06

Keywords:

A.V. Bashkirov – Dr.Sc.(Eng.), Associate Professor, Acting Head of Department Radio Equipment Engineering and Manufacturing, Voronezh State Technical University
E-mail: fabi7@mail.ru
V.M. Pitolin – Dr.Sc.(Eng.), Professor, Department «Electronics», Voronezh State Technical University
E-mail: pitol@mail.ru
I.V. Sviridova – Senior Lecturer, Department Radio Equipment Engineering and Manufacturing, Voronezh State Technical University
M.V. Khoroshailova – Assistant, Department Radio Equipment Engineering and Manufacturing, Voronezh State Technical University
E-mail: pmv2205@mail.ru


This article presents An iterative decoding architecture based on stochastic computational elements is studied. Simulation results for a (7,4) Hamming code show only about a 0.5 dB loss with respect to a belief propagationbased decoder. The critical path of the decoder is a single XOR gate, allowing it to operate at very high speed. The proposed method provides a digital, technology independent, alternative to analog decoding for high-throughput and low-power digital communications applications.
This article provides for the use of a new competitive approach for the implementation of modern LDPC codes on factor graphs. This article presents An iterative decoding architecture based on stochastic computational elements is studied. Simulation results for a (7,4) Hamming code show only about a 0.5 dB loss with respect to a belief propagationbased decoder. The critical path of the decoder is a single XOR gate, allowing it to operate at very high speed. The proposed method provides a digital, technology independent, alternative to analog decoding for high-throughput and low-power digital communications applications.
One approach that has recently attracted attention is the creation of an analog decoder by presenting the internal decoder metrics as continuous analog voltages or currents, and using analog circuits to perform decoding iterations in continuous time. For analog decoders, one or two orders of magnitude improvement in speed or power was suggested compared to their digital counterparts. In addition, the analog circuit is well suited for the relatively low accuracy requirements of iterative decoding algorithms. In this article, we present the VLSI architecture and simulation results for a decoder based on stochastic calculations. This architecture has advantages in analog decoders, but it is a technologically independent architecture that can be implemented in digital VLSI or even in FPGA. Such decoders can operate at high speeds and with low power consumption.

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